Capacitance voltage curve simulations for different passivation parameters of dielectric layers on silicon

dc.contributor.affiliationPontificia Universidad Católica del Perú. Departamento de Ciencias
dc.contributor.authorSevillano-Bendezú, M.A.
dc.contributor.authorDulanto, J.A.
dc.contributor.authorConde, L.A.
dc.contributor.authorGrieseler, R.
dc.contributor.authorGuerra Torres, J.A.
dc.contributor.authorTöfflinger, J.A.
dc.date.accessioned2026-03-13T16:57:37Z
dc.date.issued2020
dc.description.abstractAbstract Surface passivation is a widely used technique to reduce the recombination losses at the semiconductor surface. The passivating layer performance can be mainly characterized by two parameters: The fixed charge density ( Q ox ) and the interface trap density ( D it ) which can be extracted from Capacitance-Voltage measurements (CV). In this paper, simulations of High-Frequency Capacitance-Voltage (HF-CV) curves were developed using simulated passivation parameters in order to examine the reliability of measured results. The D it was modelled by two different sets of functions: First, the sum of Gaussian functions representing different dangling bond types and exponential tails for strained bonds. Second, a simpler U-shape model represented by the sum of exponential tails and a constant value function was employed. These simulations were validated using experimental measurements of a reference sample based on silicon dioxide on crystalline silicon (SiO 2 /c-Si). Additionally, a fitting process of HF-CV curves was proposed using the simple U-shape D it model. A relative error of less than 0.4% was found comparing the average values between the approximated and the experimentally extracted D it ’s. The constant function of the approximated D it represents an average of the experimentally extracted D it for values around the midgap energy where the recombination efficiency is highest.
dc.description.sponsorshipFunding: We thank Dr. Walter Füssel and Prof. César Guerra Gutierrez for the fruitful discussións. Support of the Peruvión National Council for Science, Technology and Innovación (CONCYTEC) is gratefully acknowledged: Contract N°132-2017. The authors are also thankful to the financial support given by FONDECYT through Contract N°045-2018. This research was also supported by the Research Managements Office (DGI) of the Pontificia Universidad Católica del Perú (PUCP) through grant no. CAP-2019-3-0041.
dc.identifier.doihttps://doi.org/10.1088/1742-6596/1433/1/012007
dc.identifier.urihttp://hdl.handle.net/20.500.14657/205624
dc.language.isoeng
dc.publisherInstitute of Physics
dc.relation.conferencenameJournal of Physics: Conference Series; Vol. 1433, Núm. 1 (2020)
dc.relation.ispartofurn:issn:1742-6588
dc.rightsinfo:eu-repo/semantics/closedAccess
dc.subjectSurface passivation
dc.subjectFixed charge density
dc.subjectInterface trap density
dc.subject.ocdehttps://purl.org/pe-repo/ocde/ford#2.10.00
dc.titleCapacitance voltage curve simulations for different passivation parameters of dielectric layers on silicon
dc.typehttp://purl.org/coar/resource_type/c_5794
dc.type.otherComunicación de congreso
dc.type.versionhttps://vocabularies.coar-repositories.org/version_types/c_970fb48d4fbd8a85/

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