Tesis y Trabajos de Investigación PUCP

URI permanente para esta comunidadhttp://54.81.141.168/handle/123456789/6

El Repositorio Digital de Tesis y Trabajos de Investigación PUCP aporta al Repositorio Institucional con todos sus registros, organizados por grado: Doctorado, Maestría, Licenciatura y Bachillerato. Se actualiza permanentemente con las nuevas tesis y trabajos de investigación sustentados y autorizados, así como también con los que que fueron sustentados años atrás.
Ingresa a su web: Repositorio Digital de Tesis y Trabajos de Investigación PUCP

Explorar

Filtros

20171

Ajustes

Asesorsearch.filters.applied.operator.equals: search.filters.advisor.Villota Cerna, ElizabethAutorsearch.filters.applied.operator.equals: search.filters.author.Araujo Barrientos, Antonio

Resultados de búsqueda

Mostrando 1 - 1 de 1
  • No hay miniatura disponible
    ÍtemTexto completo enlazado
    Implementation of a high performance embedded MPC on FPGA using high-level synthesis
    (Pontificia Universidad Católica del Perú, 2017-06-19) Araujo Barrientos, Antonio; Geletu, Abebe; Villota Cerna, Elizabeth
    Model predictive control (MPC) has been, since its introduction in the late 70’s, a well accepted control technique, especially for industrial processes, which are typically slow and allow for on-line calculation of the control inputs. Its greatest advantage is its ability to consider constraints, on both inputs and states, directly and naturally. More recently, the improvements in processor speed have allowed its use in a wider range of problems, many involving faster dynamics. Nevertheless, implementation of MPC algorithms on embedded systems with resources, size, power consumption and cost constraints remains a challenge. In this thesis, High-Level Synthesis (HLS) is used to implement implicit MPC algo- rithms for linear (LMPC) and nonlinear (NMPC) plant models, considering constraints on both control inputs and states of the system. The algorithms are implemented in the Zynq@ -7000 All Programmable System-on-a-Chip (AP SoC) ZC706 Evaluation Kit, targeting Xilinx’s Zynq@-7000 AP SoC which contains a general purpose Field Programmable Gate Array (FPGA). In order to solve the optimization problem at each sampling instant, an Interior-Point Method (IPM) is used. The main computation cost of this method is the solution of a system of linear equations. A minimum residual (MINRES) algorithm is used for the solution of this system of equations taking into consideration its special structure in order to make it computationally efficient. A library was created for the linear algebra operations required for the IPM and MINRES algorithms. The implementation is tested on trajectory tracking case studies. Results for the linear case show good performance and implementation metrics, as well as computation times within the considered sampling periods. For the nonlinear case, although a high computation time was needed, the algorithm performed well on the case study presented. Because of resources constraints, implementation of the nonlinear algorithm on higher order systems was precluded.